Flip chip bonding is a technique in which connections are made between a semiconductor chip and a header. Typically, bead-like projections (conductive bumps) are deposited as terminals on one face of the chip, which is then registered and bonded with header terminals disposed on a substrate module. The substrate module is commonly comprised of a ceramic material, although there is increasing interest in substrates comprised of other materials, such as plastics.
Flip chip bonding provides many advantages compared with making connections to a ceramic header using wire-bonding techniques. These advantages include a reduction in interconnection lengths; a smaller package footprint; and a lower package profile compared with conventional wire bonding techniques. Additionally, flip chip bonding techniques may permit an increased number of input/output interconnections to a chip. The flip chip bonding technique has the potential to provide connections distributed throughout the entire area of a chip with the potential number of connections for a fixed chip size being primarily limited by how densely separate solder connections can be reliably made to contact pads on the chip. In contrast, the number of input/output connections possible with conventional wire bonding is limited by how closely wire bonds can be made along the periphery of a chip.
One common flip chip bonding technique is termed the "ball grid array" mounting technique, in which a pattern of closely positioned solder balls are used to provide a flip chip connection between the chip and a ceramic substrate module. However a major concern with the ball grid array package is solder joint reliability.
As is well known in mechanical engineering, a statically determinate member (one that is free to move) comprised of a homogenous isotropic material experiences a differential increase in length for a differential increase in temperature according to the mathematical relationship: .delta..sub.T =.alpha..DELTA.TL, where .delta..sub.T is the differential increase in length of the member, .alpha. is the linear coefficient of thermal expansion, .DELTA.T is the differential change in temperature of the member, and L is the original length of the member. However, a statically indeterminate member whose thermal displacements are constrained does not change in length but instead becomes thermally stressed. It is well known that when two materials having a large mismatch between their thermal coefficients of expansion (TCE) are rigidly joined together, stresses and strains may develop in the combined structure.
This is important because there is a substantial difference in the TCE of various components of a flip chip bonding process. For example, the TCE of a semiconductor chip is typically 2.5 parts per million per degree Celsius (ppm/.degree. C.). The TCE of a ceramic substrate module is typically in the range of 10-30 ppm/.degree. C. A printed circuit (PC) board typically has a TCE of 14-20 ppm/.degree. C.
The large difference in TCE between the different components may cause substantial thermal stress. For example, an unattached ceramic module with a TCE of 25 ppm/.degree. C. and a length of 2 centimeter (cm) would expand by 30 microns for a 60.degree. C. temperature rise. By way of comparison, an unattached chip would expand by only 3 microns over the same temperature rise. However, the chip is commonly bonded to the module by solder balls, which are substantially inflexible. Consequently, thermal stresses tend to develop at the solder joints. The thermal stresses may reduce the reliability of the solder connection. In particular, the lifetime of the solder connections may be substantially reduced as a consequence of variations in stress/strain caused by thermal cycling during normal chip operation.
A solder joint which is repetitively thermally cycled may eventually fail from the cumulative effects of multiple thermal cycles. Fatigue lifetime is commonly defined as the lifetime associated with the number of applied repeated stress cycles a material can endure before failure. Generally, the fatigue lifetime of solder joints decreases with increasing thermal stress on the solder joints during each thermal cycle. Thus, the fatigue lifetime will tend to decrease as the chip size is increased and/or the temperature swing increases, because these factors increase the thermal stresses. Fatigue lifetime tends to increase somewhat when comparatively soft solder joints are utilized. A comparatively soft solder, such as a 95% lead/5% tin solder, permits some limited flexure of the solder joint, which reduces thermal stresses at the solder joints compared with a hard, inflexible solder joint. However, even with comparatively soft solder connections, the solder joints are substantially inflexible compared to the large unmounted differential expansion of the chip and substrate over common temperature swings. Large thermal stresses will tend to occur at solder joints near the edges of the chip. Consequently, the fatigue lifetime may not be as large as desirable, particularly if the chip has a comparatively large area and is thermally cycled over a large temperature range.
One attempted solution to the thermal mismatch problem is the use of an intermediate interposer layer situated between the chip and the module. An interposer typically is comprised of an insulating layer and can be used to provide separate electrical connections between solder balls on the chip and solder balls on the ceramic module. A plurality of column-like electrical conductors are disposed through the interior of the insulating layer. The column-like conductors provide electrical connections between contact pads on opposite sides of the interposer. The contact pads may be bonded to corresponding contact pads on a chip and a ceramic substrate.
Interposers may favorably alter the stress and/or strain distribution between a chip and a module. For example, an interposer may be comprised of a material with a TCE matched to that of critical solder bumps. For this case the interposer layer has the same lateral displacement response with temperature as the solder bumps. Consequently, as the device heats up the critical solder bumps will not be stressed as severely as they would be if they were directly bonded to a material that had a substantially different TCE. Alternatively, the interposer may be comprised of a material with a TCE that is intermediate in value between that of the chip and the module such that the strain associated with the lateral displacement of the module and the chip is spread out over two sets of solder balls on the top and bottom of the interposer layer.
Interposers are commonly fabricated using conventional semiconductor patterning techniques. The interposer structure is typically comprised of an insulating material whose structure and thickness render it stiff enough to be processed using conventional semiconductor fabrication techniques and to permit registration to previously patterned features. Interposers used in dense ball grid arrays, for example, may comprise a substantially flat dielectric material that substantially retains its shape during common fabrication process steps (e.g., photolithography, via hole definition, and metallization) such that contact pads and via holes may be patterned and plated on both sides of the interposer.
Commonly, interposers are comprised of a materials structure which is relatively inelastic. Although polymer films are sometimes used in interposers, typically the thickness of the polymer is comparatively thick such that substantial energy is required to achieve significant flexure of the film. Contact metals and vial hole interconnections may also further limit the transverse flexure of the interposer. In particular, some critical contact layers disposed on the surface of the interposer may include relatively low ductility metals. The low ductility metals may substantially limit the ability of the underlying insulating interposer film to flex. Also, the numerous via connections in the mounted interposer tend to "pin" the interposer film into place. Thus, the assembled structure comprised of the chip bonded to the module via the interposer comprises a substantially inflexible assembly of materials. Large thermal stresses will tend to develop as a result of the differences in TCE of the separate materials. While previously known interposers redistribute stresses caused by TCE mismatches, they do not provide a mechanism of strain relief. Consequently, the chip or module solder joints may become over stressed in device applications, such as modern computer chips, where there is substantial thermal cycling during ordinary use.
A desirable interposer structure would be compatible with the fabrication of a dense ball grid array using a high-yield fabrication process. The interposer would be of comparatively simple mechanical structure such that it could be manufactured inexpensively, with a high processing yield, and would be consistent with reliable solder joints. Additionally, the interposer structure would provide a strain relief mechanism to reduce the stress on solder joints.
What is desired is an interposer structure that permits reliable, low thermal-stress flip chip bonding of a semiconductor chip to a module.